Thresholding Decision-Directed Descent (T3D): A Tuning Solution for DDR5 DRAM DFEs

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-08-06 DOI:10.1109/TVLSI.2024.3435419

Mitchell Cooke;Nicola Nicolici

引用次数: 0

Abstract

Emerging memory technologies, such as DDR5, offer increased data rates and storage capacities, at the expense of signal integrity challenges. To address these challenges, the DDR5 standard incorporates a four-tap decision feedback equalizer (DFE). As elaborated in this article, known methods for DFE tuning are limited due to interface complexity and distinct equalization requirements for DDR5. We propose a decision-directed DFE tuning method called thresholding decision-directed descent (T3D). By leveraging DDR5 architectural features, our novel method tracks the eye envelope as it opens, which facilitates rapid convergence compared to the state of the art. To validate the performance of T3D, silicon measurements are presented alongside a virtual testbench methodology. By demonstrating the high correlation between silicon and simulation results, the virtual testbench can be beneficial for the design, validation, and prototyping of future DFE tuning methods.

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阈值决策定向下降 (T3D)：DDR5 DRAM DFE 的调整解决方案

DDR5 等新兴内存技术提高了数据传输速率和存储容量，但也带来了信号完整性方面的挑战。为了应对这些挑战，DDR5 标准采用了四抽头决策反馈均衡器（DFE）。正如本文所阐述的，由于接口的复杂性和 DDR5 独特的均衡要求，已知的 DFE 调整方法受到了限制。我们提出了一种称为阈值决策定向下降（T3D）的决策定向 DFE 调整方法。通过利用 DDR5 架构特性，我们的新方法可在眼球包络打开时跟踪眼球包络，与现有技术相比，收敛速度更快。为了验证 T3D 的性能，在介绍虚拟测试台方法的同时，还介绍了硅测量结果。通过证明硅片和仿真结果之间的高度相关性，虚拟测试台有助于未来 DFE 调整方法的设计、验证和原型开发。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.