A Low-Cost Quadruple-Node-Upsets Resilient Latch Design

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-29 DOI:10.1109/TVLSI.2024.3430224

Luchang He;Chenchen Xie;Qingyu Wu;Siqiu Xu;Houpeng Chen;Xing Ding;Xi Li;Zhitang Song

引用次数: 0

Abstract

In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback loops, ensuring complete resilience to quadruple-node upsets (QNUs). Each Sim comprises ten CMOS transistors and a clocked inverter. Notably, C-element (CE) and dual interlocked storage cell (DICE) modules are not employed in this circuit, resulting in a small area and low power consumption. The simulation results verify the complete QNU self-recoverability and cost-effectiveness of this design. Compared with the existing radiation-hardened QNU resilient latches, the LCQRL latch demonstrates significant improvements in area, power consumption, and area-power–delay product (APDP) by 47.8%, 63%, and 75.5%, respectively. Furthermore, it exhibits low sensitivity to process, voltage, and temperature (PVT) variations.

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低成本四重节点镦粗弹性锁存器设计

本文提出了一种低成本四节点复位弹性锁存器（LCQRL）设计。为了满足安全关键型应用的高可靠性要求，该锁存器集成了九个软误差感知模块（SIM），以形成稳健的反馈回路，确保对四节点中断（QNU）具有完全的恢复能力。每个 SIM 由十个 CMOS 晶体管和一个时钟反相器组成。值得注意的是，该电路没有采用 C 元素（CE）和双互锁存储单元（DICE）模块，因此面积小、功耗低。仿真结果验证了该设计的完整 QNU 自恢复能力和成本效益。与现有的辐射加固型 QNU 弹性锁存器相比，LCQRL 锁存器在面积、功耗和面积-功耗-延迟积（APDP）方面都有显著改善，分别提高了 47.8%、63% 和 75.5%。此外，它对工艺、电压和温度（PVT）变化的敏感性也很低。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.