Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors

Abstract

In the relentless pursuit of semiconductor device scaling, stacked silicon nanosheet gate-all-around field-effect transistors (NSFETs) are emerging as key candidates for sub-3nm technology nodes. However, the challenge of channel leakage in these devices is critical and necessitates innovative solutions. A novel SDE asymmetric counter-doping technique is proposed in this study. It investigates the impact of source/drain extension on device performance using different process schemes through three-dimensional technical computer-aided design (3D TCAD) simulations. The simulations demonstrate a comprehensive technically advantages for 25.2 %/16.65 % reduction in the off-state leakage, 27.36 %/15.03 % improvement in the on-off current ratio of N/P NSFETs, respectively. Furthermore, it shows more performance gain as the gate length scaling beyond 3 nm technology nodes. The compatibility of the asymmetric counter-doping method with mainstream NSFET integration flows and its scalability to 10 nm gate lengths indicate that it is a promising approach to optimize NSFETs performance with little extra process cost.