N-DIBL optimization of NC-GAAFET NW for low power fast switching applications

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2024-07-24 DOI:10.1016/j.mejo.2024.106321

Vivek Kumar, Ravindra Kumar Maurya, Kavicharan Mummaneni

{"title":"N-DIBL optimization of NC-GAAFET NW for low power fast switching applications","authors":"Vivek Kumar, Ravindra Kumar Maurya, Kavicharan Mummaneni","doi":"10.1016/j.mejo.2024.106321","DOIUrl":null,"url":null,"abstract":"<div>Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger ION and IOFF is significantly reduced by ⁓105 orders, which is due NC effect, compared to baseline NW. SSavg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (tfe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at tfe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000250","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

Abstract

Gate-all-around field effect transistors (GAAFETs), exhibit improved SCEs, are proposed to replace conventional FinFET in scaled nanodevices owing to excellent gate control. The voltage scaling concept is embodied in negative capacitance (NC) which provides same on current at reduced voltage. The proposed NC-GAAFET yields 5.31 times larger I_ON and I_OFF is significantly reduced by ⁓10⁵ orders, which is due NC effect, compared to baseline NW. SS_avg for the NC-GAAFET is 33mV/dec which surpasses Boltzmann tyranny and manifests steep subthreshold behavior. Effect of FE thickness (t_fe) variations on DIBL has been explored and found to be negative, which improves SCEs. The negative-DIBL for device has been found to be −20 mV/V at t_fe = 6 nm. Furthermore, a CMOS inverter circuit employing the NC-GAAFET has been presented that provides an average propagation delay of 174 fS which is 47 % lesser as compared to that of baseline device. The NC-GAAFET NW findings fulfill the quest of low power fast switching device for digital applications.

查看原文本刊更多论文

针对低功耗快速开关应用的 NC-GAAFET NW 的 N-DIBL 优化

栅极周围场效应晶体管（GAAFET）具有更好的 SCE，由于其出色的栅极控制能力，建议在按比例放大的纳米器件中取代传统的 FinFET。电压缩放概念体现在负电容（NC）上，它能在降低电压时提供相同的导通电流。与基线 NW 相比，拟议的 NC-GAAFET 产生的 ION 增大了 5.31 倍，IOFF 显著降低了⁓105 级，这是 NC 效应的结果。NC-GAAFET 的 SSavg 为 33mV/dec，超过了玻尔兹曼定律，并表现出陡峭的阈下行为。我们还探讨了 FE 厚度 (tfe) 变化对 DIBL 的影响，发现 DIBL 为负值，从而改善了 SCE。在 tfe = 6 nm 时，器件的负 DIBL 为 -20 mV/V。此外，还介绍了一种采用 NC-GAAFET 的 CMOS 逆变器电路，其平均传播延迟为 174 fS，比基准器件的延迟时间短 47%。NC-GAAFET NW 的发现满足了数字应用对低功耗快速开关器件的需求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.