Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET

Abstract

This research work evaluates a performance analysis of heterostructure (SiGe/Si) double gate extended source Tunnel FET (Hetero-ES-TFET) to enhance the analog performance, linearity and noise performance. At the source-channel junction, a Hetero-ES-TFET's source is extended into the channel to increase point and line tunneling in the device. The Hetero-ES-TFET exhibits a high I_ON/I_OFF of 3.57 × 10¹² and a maximum cut off frequency f_T of 54.19 GHz for optimization of device structural parameters. This analysis is conducted using a calibrated SILVACO, technology computer-aided design (TCAD) simulator. The proposed structure includes evaluation of linearity and noise performance characteristics. Furthermore, a linearity analysis as a figure of merit was conducted for the proposed device under study, including different parameters such as 3^rd order intermodulation distortion point (IMD₃), 3^rd order intermodulation intercept point (IIP₃), 2^nd and 3^rd order voltage intercept point (VIP₂ and VIP₃). The proposed Hetero-ES-TFET has achieved an incredibly high ON current and low threshold voltage. The effect of increasing source width has been examined in this work while sub-threshold swing (SS) remains unchanged during the analysis. There is an improvement in threshold voltage and I_ON/I_OFF value by using silicon-germanium (SiGe) as a source material.