Kazuki Tomigahara, Masahiro Hara, M. Nozaki, Takuma Kobayashi, Heiji Watanabe
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引用次数: 0
Abstract
In this study, impacts of post-deposition annealing (PDA) on hole trap generation at SiO2/p-GaN MOS interfaces are investigated. While the surface potential is strongly pinned due to severe hole trapping after 800°C PDA, successful hole accumulation is observed when PDA is performed at 200°C. The density of interface hole traps causing surface potential pinning, extracted from the hump in capacitance-voltage curves, is about 1012 cm−2 with 200°C PDA, while over 1013 cm−2 when the PDA temperature exceeds 600°C, regardless of the annealing ambient. Consequently, the origin of these hole traps is speculated to be defects generated by thermal effects.
期刊介绍:
Applied Physics Express (APEX) is a letters journal devoted solely to rapid dissemination of up-to-date and concise reports on new findings in applied physics. The motto of APEX is high scientific quality and prompt publication. APEX is a sister journal of the Japanese Journal of Applied Physics (JJAP) and is published by IOP Publishing Ltd on behalf of the Japan Society of Applied Physics (JSAP).