Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-25 DOI:10.1109/TVLSI.2024.3426516

M. Ghashghai;M. B. Ghaznavi-Ghoushchi

{"title":"Design and Analysis of a New Three-Stage Feedback Amplifier Utilizing Signal Flow Graph Domain Inspection Approach","authors":"M. Ghashghai;M. B. Ghaznavi-Ghoushchi","doi":"10.1109/TVLSI.2024.3426516","DOIUrl":null,"url":null,"abstract":"In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n CMOS standard technology with 0.004-mm2 active area and 8.8-\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C\n<inline-formula> <tex-math>$_{\\text {L}} =3.7$ </tex-math></inline-formula>\n nF. An average slew rate (SR) of 0.38 v/\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10609834/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}

引用次数: 0

Abstract

In this article, the design strategy with the analysis in the graph domain and changing the signal flow graph (SFG) of an amplifier are employed according to the graph rules at the system level. A three-stage amplifier, which expands the dual-path structure and buffering-based pole relocation amplifier through the graph domain inspection by using the graph rules, is proposed. By adding order of denominator in main fraction of the equivalent impedance of active zero block, the proposed amplifier can effectively increase the driving ability while enhancing the amplifier’s stability for a large range of capacitive load. The second pole is located at a higher frequency to increase the phase margin (PM). Circuit implementation of the proposed amplifier is simulated in 0.18-

$\mu $

CMOS standard technology with 0.004-mm2 active area and 8.8-

$\mu $

power consumption. Post-layout simulation results show 130 dB in dc gain, with a 670-kHz unity-gain frequency, while the amplifier uses a 400-fF compensation capacitor. The amplifier has obtained a PM of 60.4° at C

$_{\text {L}} =3.7$

nF. An average slew rate (SR) of 0.38 v/

$\mu $

s was measured when the proposed amplifier was in unity-gain configuration to drive a 3.7-nF load capacitor. FoMS and FoML in the proposed amplifier are improved by 116% and 107%, respectively.

查看原文本刊更多论文

利用信号流图域检测法设计和分析新型三级反馈放大器

本文采用图域分析的设计策略，并根据系统级的图规则改变放大器的信号流图（SFG）。本文提出了一种三级放大器，它通过图域检验，利用图规则扩展了双通道结构和基于缓冲的极点重置放大器。通过增加有源零块等效阻抗主分数分母的阶次，所提出的放大器可以有效提高驱动能力，同时增强放大器在大范围电容负载下的稳定性。第二极位于较高频率，以增加相位裕度（PM）。在 0.004 平方米有源面积和 8.8 美元功耗的 0.18 美元 CMOS 标准技术中模拟了拟议放大器的电路实现。布局后仿真结果显示，直流增益为 130 dB，单增益频率为 670 kHz，而放大器使用了 400-fF 补偿电容器。在 C $_{\text {L}} =3.7$ nF 时，放大器的 PM 为 60.4°。当该放大器采用单增益配置驱动 3.7 nF 负载电容器时，测得平均压摆率 (SR) 为 0.38 v/ $\mu $ s。拟议放大器的 FoMS 和 FoML 分别提高了 116% 和 107%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.