ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-17 DOI:10.1109/TVLSI.2024.3411033

Jonti Talukdar;Woo-Hyun Paik;Eduardo Ortega;Krishnendu Chakrabarty

引用次数: 0

Abstract

We present a logic ambiguity-based intellectual property (IP) obfuscation method that replaces traditional key gates with key-controlled functionally ambiguous logic gates, called LGA gates. We also protect timing paths by developing timing-ambiguous sequential cells called TA cells. We call this locking scheme ambiguous logic and timing logic locking (referred to as ALT-Lock). ALT-Lock ensures a two-pronged system-level security scheme where the attacker is forced to unlock not only combinational logic obfuscation but also timing obfuscation. We show that a combination of logic and timing ambiguity (TA) provides security against oracle-guided attacks. This method is superior to other traditional IP protection schemes such as combinational or sequential locking as it guarantees security against both oracle-guided and oracle-free attacks, while ensuring low power, performance, and area (PPA) overhead.

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ALT-Lock：基于逻辑和时序模糊性的 IP 混淆技术对抗逆向工程

我们提出了一种基于逻辑模糊性的知识产权（IP）混淆方法，用密钥控制的功能模糊逻辑门（称为 LGA 门）取代传统的密钥门。我们还通过开发称为 TA 单元的时序模糊单元来保护时序路径。我们将这种锁定方案称为模糊逻辑和时序逻辑锁定（简称 ALT-Lock）。ALT-Lock 确保了一种双管齐下的系统级安全方案，攻击者不仅要解锁组合逻辑混淆，还要解锁时序混淆。我们表明，逻辑和时序模糊性（TA）的结合可提供抵御甲骨文引导攻击的安全性。这种方法优于其他传统的知识产权保护方案，如组合锁定或顺序锁定，因为它既能保证对甲骨文引导攻击和无甲骨文攻击的安全性，又能确保较低的功耗、性能和面积（PPA）开销。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.