Gain and Power Enhancement With Coupled Technique for a Distributed Power Amplifier in 0.25- μm GaN HEMT Technology

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-17 DOI:10.1109/TVLSI.2024.3411143

Xu Yan;Jingyuan Zhang;Guansheng Lv;Wenhua Chen;Yongxin Guo

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引用次数: 0

Abstract

In this article, a fully integrated 1.0–11.0-GHz wideband distributed power amplifier (DPA) monolithic microwave integrated circuit (MMIC) design is presented. Particularly, a coupled technique with bandpass (CTB) characteristic between the kth output node and the (

$k+1$

)th input node of amplification units (AUs) is adopted in the DPA design. It generates an additional signal reuse path (SRP) to reuse part of the output signal to superimpose the input signal, and then they will be reamplified to the output artificial transmission line (O-ATML). Moreover, due to the bandpass characteristic, the signal reuse can be manipulated to target the upper cutting edges of the working band to alleviate sharp gain and power roll-off. By carefully controlling the SRP, the overall gain, output power, and bandwidth are enhanced and extended. The systematic design approach for the DPA is detailed with circuit implementations and optimizations. To validate the proposed concept, a DPA MMIC prototype is implemented and fabricated in a commercial 0.25-

$\mu $

m gallium nitride (GaN)-on-silicon carbide (SiC) high-electron-mobility transistor (HEMT) process. It shows the compact layout within a die size of 3.36 mm2. Under 28-V VDD power supply, the measured results show a flat

$14.8\pm 1.0$

-dB small-signal gain with 10.0-GHz wide operating bandwidth and good impedance matching conditions. A saturated output power (

${P} _{\text {sat}}$

) of 7.25 W with peak power-added efficiency (PAE) exceeding 38.7% is achieved. The proposed DPA obtains around 1.54–2.16-W/mm2 power density associated with an average PAE of 34.5% over the entire frequency range.

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利用耦合技术提高 0.25 μm GaN HEMT 技术分布式功率放大器的增益和功率

本文介绍了一种全集成的 1.0-11.0-GHz 宽带分布式功率放大器（DPA）单片微波集成电路（MMIC）设计。特别是，在 DPA 设计中，第 k 个输出节点与放大单元（AU）的 ( $k+1$ )th 输入节点之间采用了具有带通（CTB）特性的耦合技术。它产生一个额外的信号重用路径（SRP），重用部分输出信号来叠加输入信号，然后将它们重新放大到输出人工传输线（O-ATML）。此外，由于带通特性，信号重用可以针对工作频带的上切边进行操作，以减轻急剧的增益和功率滚降。通过仔细控制 SRP，整体增益、输出功率和带宽都得到了增强和扩展。本文详细介绍了 DPA 的系统设计方法、电路实现和优化。为了验证所提出的概念，在商用 0.25- $\mu $ m 氮化镓（GaN）-碳化硅（SiC）高电子迁移率晶体管（HEMT）工艺中实现并制造了一个 DPA MMIC 原型。它显示了 3.36 平方毫米芯片尺寸内的紧凑布局。在 28 V VDD 供电条件下，测量结果显示具有 14.8/pm 1.0$ -dB 的平坦小信号增益、10.0-GHz 宽工作带宽和良好的阻抗匹配条件。饱和输出功率（${P} _{text\ {sat}}$ ）为 7.25 W，峰值功率附加效率（PAE）超过 38.7%。在整个频率范围内，拟议的 DPA 功率密度约为 1.54-2.16-W/mm2，平均 PAE 为 34.5%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.