A PLL‐less grid‐tied three‐phase multilevel inverter with reduced device count and LCL filter

Abstract

This paper introduces a novel three‐phase grid‐tied multilevel inverter (MLI) topology that employs a basic unit per phase, yielding a symmetrical configuration capable of generating five‐level output voltage and an asymmetrical configuration producing seven‐level and nine‐level output voltages. The generalization of the proposed MLI is presented in terms of the number of modules (M) and output levels (L). A comprehensive comparative analysis of the proposed MLI topology against existing configurations is presented for both symmetric and asymmetric cases. The switching devices in the MLI are controlled using the in‐phase disposition level shift PWM (IPD‐LSPWM) technique. The synchronization of the grid‐tied MLI is addressed by considering the uncertainties in grid and load parameters at the point of common coupling (PCC). To achieve synchronization, a PLL‐less grid voltage‐ modulated direct power control (GVM‐DPC) technique is implemented. To mitigate the delay associated with PLL, a GVM‐DPC based on the stationary reference frame (SRF) is applied. This paper also includes mathematical modelling of GVM‐DPC without PLL and the design of an LCL filter. A simulation model of a 15‐kVA, three‐phase, nine‐level grid‐tied MLI is developed in MATLAB/Simulink and tested under both steady‐state and dynamic conditions. The proposed controller's performance is evaluated under the load variations and sudden changes in available power from the distributed generator (DG). Robustness is tested under adverse conditions such as voltage sag/swell at the PCC. Furthermore, the system is implemented in the OPAL‐RT OP4510 real‐time simulator, and the results are validated to confirm the effectiveness and robustness of the proposed grid‐tied MLI.