A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

Abstract

Analog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.