Design Space Optimization for Eradication of NDR Effect in Dielectric/Ferroelectric Stacked Negative Capacitance Multi-Gate FETs at Sub-3nm Technology for Digital/Analog/RF Applications

IF 2.9 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Dielectrics and Electrical Insulation Pub Date : 2024-07-22 DOI:10.1109/tdei.2024.3432088

Sresta Valasa, Venkata Ramakrishna Kotha, Shubham Tayal, Narendar Vadthiya

引用次数: 0

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优化设计空间，消除 3 纳米以下技术中用于数字/模拟/射频应用的介电/费电叠层负电容多栅极场效应晶体管中的 NDR 效应

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Dielectrics and Electrical Insulation 工程技术-工程：电子与电气

CiteScore

6.00

自引率

22.60%

发文量

309

审稿时长

5.2 months

期刊介绍： Topics that are concerned with dielectric phenomena and measurements, with development and characterization of gaseous, vacuum, liquid and solid electrical insulating materials and systems; and with utilization of these materials in circuits and systems under condition of use.