All-oxide transistors for vertical stacking

IF 33.7 1区工程技术 Q1 ENGINEERING, ELECTRICAL & ELECTRONIC

Nature Electronics Pub Date : 2024-07-22 DOI:10.1038/s41928-024-01223-y

Katharina Zeissler

引用次数: 0

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用于垂直堆叠的全氧化物晶体管

内存计算可用于提高能效，但需要高密度的存储单元。在保持相同占地面积的情况下提高存储密度的一种方法是将存储单元堆叠在一起。虽然使用传统半导体（如多晶硅）可以实现堆叠，但制造方面的挑战（如侧壁均匀性、掺杂剖面变化、高热预算和金属扩散）会对性能产生负面影响。普渡大学和三星电子公司的研究人员通过原子层沉积制造了这种器件。他们使用超薄氧化铟（In2O3）层作为沟道，使用厚的变性氧化铟层作为栅极，从而避免了金属或氮化物金属栅极制造工艺中通常会出现的金属扩散现象。该工艺还可用于制造铁电场效应晶体管，其内存窗口为 1.85 V，开/关比率为 104，保持时间为 10 年，耐久性超过 109 个周期。

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来源期刊

Nature Electronics Engineering-Electrical and Electronic Engineering

CiteScore

47.50

自引率

2.30%

发文量

159

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