Functionally Possible Path Delay Faults With High Functional Switching Activity

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-16 DOI:10.1109/TVLSI.2024.3425817

Irith Pomeranz;Yervant Zorian

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引用次数: 0

Abstract

Chip aging that results in small delay defects is one of the possible causes for silent data corruption that has been observed in large datacenters. Chip aging is exacerbated by high software workloads when the chip is deployed in a system. Small delay defects are detected by tests for path delay faults. Path delay faults are typically selected to include the longest testable paths. In addition, functionally possible paths are selected to ensure the detection of small delay defects that can cause a chip to fail during functional operation. To address chip aging, it is suggested in this brief that the longest functionally possible paths through as many lines as possible with the highest susceptibilities to aging should be targeted. A path selection procedure at the gate level is described, that uses the switching activity under functional test sequences to identify functionally possible paths that are the most susceptible to aging. Experimental results for benchmark circuits show that the length of a path and the functional switching activities for lines along the path are independent, and each criterion alone leads to the selection of different paths. The results suggest that both criteria need to be used together for path selection.

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功能开关活动频繁时可能出现的路径延迟故障

在大型数据中心观察到的静默数据损坏现象中，导致小延迟缺陷的芯片老化是可能的原因之一。在系统中部署芯片时，高软件工作量会加剧芯片老化。小延迟缺陷可通过路径延迟故障测试检测出来。路径延迟故障的选择通常包括最长的可测试路径。此外，还要选择功能上可能的路径，以确保检测到可能导致芯片在功能运行期间失效的小延迟缺陷。为解决芯片老化问题，本简介建议应尽可能多地选择最长的功能可能路径，这些路径应是最容易老化的线路。本文介绍了一种门级路径选择程序，该程序利用功能测试序列下的开关活动来识别最易老化的功能可能路径。基准电路的实验结果表明，路径长度和路径沿线的功能开关活动是相互独立的，单凭这两项标准就能选择不同的路径。结果表明，在选择路径时需要同时使用这两个标准。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.