Design of RISC-V out-of-order processor based on segmented exclusive or Gshare branch prediction

Abstract

To address the balanced requirements of performance, power consumption, and area in embedded systems, this paper introduces a 32-bit out-of-order processor based on the RISC-V instruction set, and the processor supports interrupt handling. This processor is designed to support the RV32IMC instruction subset and utilizes a four-stage pipeline structure featuring sequential instruction fetching, out-of-order execution, and out-of-order write-back. The main contributions are as follows:1) The segmented exclusive or G-share branch prediction scheme for embedded processors is proposed, which provides high branch prediction accuracy when the capacity of pattern history table (PHT) is small. 2) The work undertaken by hardware and software during interrupt response is reasonably divided, which allows for fast interrupt response with minimal resource consumption. Furthermore, the interrupt response time in vectored mode is reduced by simultaneously stacking the control and status registers (CSRs) and obtaining the interrupt service routine (ISR) entry address. Executing branch prediction-related programs within an identical environment, the processor detailed in this paper demonstrates an average prediction accuracy improvement of 1.2 % over G-share and 0.6 % over bi-mode branch prediction when employing the segmented exclusive or G-share branch prediction scheme. Building on this foundation, the on-chip debugging system and memory management unit have been implemented. The processor reaches 1.389 Dhrystone/MHz and 2.802 Coremark/MHz.