TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

Abstract

The study aimed to investigate the transfer characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our device simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.