Establishing On-Wafer Calibration Standards for the 16-Term Error Model: Application to Silicon High-Frequency Transistor Characterization

Abstract

This work focuses on a novel methodology to establish on-wafer calibration standards for the 16-Term Error Calibration Technique. It combines TRL-calibrated data with EM simulation to precisely generate S-parameters of standards. Applied to the advanced BiCMOS 55 nm technology, with a layout maintaining consistent coupling between standards, the 16 error-terms calibration results in significant improvements from 40 GHz onward compared to standard calibration (SOLT or TRL) techniques. Notably, it corrects probe couplings, eliminates discontinuities between frequency bands, and ensures the accuracy of S-parameter measurements. Unlike traditional SOLT and TRL methods, this new approach attributes measured quantities solely to intrinsic transistor behavior.