{"title":"A high constancy and noise suppression voltage shift generator in SEIR-based BIST circuit for ADC linearity test","authors":"","doi":"10.1016/j.mejo.2024.106341","DOIUrl":null,"url":null,"abstract":"<div><p>—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9000,"publicationDate":"2024-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239124000456","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
—The built-in self-test (BIST) circuit is designed to be highly integrated with ADC under test and tests the static linearity based on the stimulus error identification and removal (SEIR) method. A novel level shift generator is proposed for high-precision ADC testing to break the resolution limitation caused by thermal noise and non-linearity. The double sampling operation realized by the chopper circuits cancels the sampling kT/C noise, and the circuit further reduces the amplifier's thermal noise by reducing the noise bandwidth. Besides, this paper presents a new method to achieve a highly linearity-constant voltage shift by applying the negative-C technique. Implemented in 180 nm CMOS process, the simulation results show that the noise power of the voltage shift is reduced by 10 dB, and the constancy of voltage shift is only 3.7 ppm over the entire ADC input range. Benefitting from the noise and linearity performance enhancement, this BIST circuit can test 18-bit ADC to 18-bit accuracy level with one-tenth sampling points.
期刊介绍：
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc.
Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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