A nMOS-R Cross-Coupled Level Shifter With High dV/dt Noise Immunity for 600-V High-Voltage Gate Driver IC

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-07-12 DOI:10.1109/TVLSI.2024.3417385

Yu Lu;Xiaowu Cai;Jian Lu;Longli Pan;Jianying Dang;Yafei Xie;Xupeng Wang;Bo Li

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引用次数: 0

Abstract

In digital integrated circuits with multiple power domains, level shifters (LSs) are essential circuit elements that can transform the voltage region from low to high. However, high-frequency gate drivers can generate hundreds of voltages per nanosecond noise (high dV/dt noise). Such high dV/dt noise can cause malfunction of a conventional pulse-triggered cross-coupled LS (CCLS) that is used to control the high-side nMOS switch. In this article, a novel LS with noise immunity is proposed and investigated. Compared with the conventional resistor load LS, the proposed circuit adopts nMOS-R cross-coupled (NRCC) LS, and realizes the selective filtering ability by exploiting the path that filters out the noise introduced by the dV/dt. The high-voltage gate drive integrated circuit (HVIC) is implemented using a 600 V silicon-on-insulator (SOI) BCD process. Analyses and experiments show that the proposed design can help the HVIC maintain a high common-mode transient immunity (CMTI) of up to 137 V/ns while allowing a negative VS swing down to -9.4 V under a 15 V supply voltage. Compared with the traditional HVIC with resistance load LS, the proposed novel HVIC with the NRCC LS improves the noise immunity of dV/dt by 182%.

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用于 600 V 高压栅极驱动器集成电路、具有高 dV/dt 抗噪能力的 nMOS-R 交叉耦合电平转换器

在具有多个功率域的数字集成电路中，电平转换器（LS）是将电压区域从低电平转换到高电平的重要电路元件。然而，高频栅极驱动器每纳秒可产生数百个电压噪声（高 dV/dt 噪声）。这种高 dV/dt 噪声会导致用于控制高压侧 nMOS 开关的传统脉冲触发交叉耦合 LS（CCLS）出现故障。本文提出并研究了一种具有抗噪能力的新型 LS。与传统的电阻负载 LS 相比，所提出的电路采用了 nMOS-R 交叉耦合 (NRCC) LS，并通过利用滤除 dV/dt 引入的噪声的路径实现了选择性滤波能力。高压栅极驱动集成电路（HVIC）采用 600 V 硅绝缘体（SOI）BCD 工艺实现。分析和实验表明，所提出的设计可帮助 HVIC 保持高达 137 V/ns 的高共模瞬态抗扰度 (CMTI)，同时允许在 15 V 电源电压下实现低至 -9.4 V 的负 VS 摆幅。与采用电阻负载 LS 的传统 HVIC 相比，采用 NRCC LS 的新型 HVIC 将 dV/dt 的抗噪能力提高了 182%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.