Matching constraint extraction for analog integrated circuits layout via edge classify

Abstract

Achieving matching constraints between various components is important in analog integrated circuit (IC) layout design, as it can reduce the impact of layout parasitics on the performance of IC. When automating analog integrated circuit layout design, identifying accurate matching constraints is an essential step before placement and routing. The matching relationship between devices strongly depends on circuit's topology and design expertise. This work focuses on differential circuits with various topologies and proposes a supervised learning framework that incorporates symmetry analysis. The heterogeneous multi-relationship graph representation is proposed to capture circuit's topology and extract matching constraints. Additionally, a symmetry analysis algorithm and filtering method based on matching levels are investigated to enhance the model's performance. The experimental results demonstrate that this work maintains a low false alarm rate and outperforms other matching constraint detection algorithms in terms of F₁ score and accuracy.