High-performance anti-series diode ring amplifier for switched capacitor circuits

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-07-08 DOI:10.1016/j.vlsi.2024.102236

Anmol Verma, Shubhang Srivastava, Shivam Bhardwaj, Ambika Prasad Shah

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引用次数: 0

Abstract

Ring amplifiers enable efficient amplification with less power consumption. These are characterized by fairly power requirements, and innate rail-to-rail output swing and are robust against PVT variations. In this paper, we are presenting an improved self-biased anti-series diode-based ring amplifier (ASD-RAMP) design, implemented on 45-nm CMOS technology. The design uses two diode-connected PMOS transistors that are connected in an anti-series manner to generate a large resistance because of which a high dead-zone voltage is generated. The ASD-RAMP has a settling time of only 4.05 ns, which is nearly half of the conventional self-biased ring amplifier (CSB-RAMP). In comparison to CSB-RAMP, the proposed ASD-RAMP improves the dead-zone voltage by $1.1 \times$ while requiring 6.76% less power. The circuit is durable and suitable for high-performance applications since it exhibits great resilience to PVT variations in addition to the improved dead zone voltage and reduced settling time.

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用于开关电容器电路的高性能反串二极管环形放大器

环形放大器能以更低的功耗实现高效放大。环形放大器的特点是功耗要求低，具有天生的轨至轨输出摆幅，并能抵御 PVT 变化。本文介绍了一种改进的自偏压反串二极管环形放大器（ASD-RAMP）设计，采用 45 纳米 CMOS 技术实现。该设计使用两个二极管连接的 PMOS 晶体管，以反串联方式连接，从而产生一个大电阻，并由此产生一个高死区电压。ASD-RAMP 的沉淀时间仅为 4.05 ns，几乎是传统自偏压环形放大器 (CSB-RAMP) 的一半。与 CSB-RAMP 相比，所提出的 ASD-RAMP 将死区电压提高了 1.1 倍，同时功耗降低了 6.76%。该电路经久耐用，适用于高性能应用，因为除了提高死区电压和缩短沉淀时间外，它还能很好地抵御 PVT 变化。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.