Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Kasra Ahmadi;Saeed Aghapour;Mehran Mozaffari Kermani;Reza Azarderakhsh
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引用次数: 0

Abstract

Elliptic curve scalar multiplication (ECSM) is a fundamental element of public key cryptography. The ECSM implementations on deeply embedded architectures and Internet-of-nano-Things have been vulnerable to both permanent and transient errors, as well as fault attacks. Consequently, error detection is crucial. In this work, we present a novel algorithm-level error detection scheme on Montgomery Ladder often used for a number of elliptic curves featuring highly efficient point arithmetic, known as Montgomery curves. Our error detection simulations achieve high error coverage on loop abort and scalar bit flipping fault model using binary tree data structure. Assuming n is the size of the private key, the overhead of our error detection scheme is $O(n)$ . Finally, we conduct a benchmark of our proposed error detection scheme on both ARMv8 and field-programmable gate array (FPGA) platforms to illustrate the implementation and resource utilization. Deployed on Cortex-A72 processors, our proposed error detection scheme maintains a clock cycle overhead of less than 5.2%. In addition, integrating our error detection approach into FPGAs, including AMD/Xilinx Zynq Ultrascale+ and Artix Ultrascale+, results in a comparable throughput and less than 2% increase in area compared with the original hardware implementation. We note that we envision using adoptions of the proposed architectures in the postquantum cryptography (PQC) based on elliptic curves.
在 FPGA 上以蒙哥马利梯形图为基准的高效错误检测密码体系结构
椭圆曲线标量乘法(ECSM)是公钥密码学的基本要素。在深度嵌入式架构和纳米物联网上实现的 ECSM 容易受到永久和瞬时错误以及故障攻击的影响。因此,错误检测至关重要。在这项工作中,我们针对蒙哥马利梯形图(Montgomery Ladder)提出了一种新颖的算法级错误检测方案,这种梯形图通常用于一些具有高效点运算功能的椭圆曲线,即蒙哥马利曲线。我们的错误检测模拟利用二叉树数据结构,在循环中止和标量位翻转故障模型上实现了高错误覆盖率。假设 n 是私钥的大小,我们的错误检测方案的开销为 $O(n)$。最后,我们在 ARMv8 和现场可编程门阵列(FPGA)平台上对我们提出的错误检测方案进行了基准测试,以说明其实现和资源利用情况。在 Cortex-A72 处理器上部署我们提出的错误检测方案后,时钟周期开销保持在 5.2% 以下。此外,将我们的错误检测方法集成到 FPGA(包括 AMD/Xilinx Zynq Ultrascale+ 和 Artix Ultrascale+)中,与原始硬件实现相比,吞吐量相当,面积增加不到 2%。我们注意到,我们设想在基于椭圆曲线的后量子密码学(PQC)中采用所提出的架构。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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