A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Meenali Janveja;Rushik Parmar;Srichandan Dash;Jan Pidanic;Gaurav Trivedi
{"title":"A Low-Power Co-Processor to Predict Ventricular Arrhythmia for Wearable Healthcare Devices","authors":"Meenali Janveja;Rushik Parmar;Srichandan Dash;Jan Pidanic;Gaurav Trivedi","doi":"10.1109/TVLSI.2024.3413584","DOIUrl":null,"url":null,"abstract":"Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least \n<inline-formula> <tex-math>$15 \\ \\min $ </tex-math></inline-formula>\n before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes \n<inline-formula> <tex-math>$4.69~\\mu \\text { W}$ </tex-math></inline-formula>\n when implemented using SCL \n<inline-formula> <tex-math>$180\\text {-nm}$ </tex-math></inline-formula>\n bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10589544/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

Ventricular arrhythmia (VA) is the most critical cardiac anomaly among all arrhythmia beats. Thus, it becomes imperative to predict the occurrence of VA to avoid sudden casualties caused by these arrhythmia beats. In the past, only a few hardware designs have been proposed to predict VA using various features derived from electrocardiogram (ECG) signals and processed using machine learning classifiers. However, these designs are either complex or need more prediction accuracy. Therefore, a deep neural network (DNN)-based co-processor for arrhythmia prediction is proposed in this article. It can predict VA at least $15 \ \min $ before its occurrence with 91.6% accuracy. Co-processor architecture for arrhythmia prediction (CoAP) uses an optimal feature vector extracted from the ECG signal and an optimized DNN, using a novel approximate multiplier (AM). CoAP operates at 12.5 kHz and consumes $4.69~\mu \text { W}$ when implemented using SCL $180\text {-nm}$ bulk CMOS technology. The low power realization of the proposed design and its higher accuracy, compared with well-known state-of-the-art methods, make it suitable for wearable devices.
为可穿戴医疗设备预测室性心律失常的低功耗协处理器
室性心律失常(VA)是所有心律失常中最严重的心脏异常。因此,当务之急是预测室性心律失常的发生,以避免这些心律失常搏动造成的突发伤亡。过去,只有少数几种硬件设计可利用从心电图(ECG)信号中提取的各种特征并通过机器学习分类器进行处理来预测 VA。然而,这些设计要么复杂,要么需要更高的预测精度。因此,本文提出了一种基于深度神经网络(DNN)的心律失常预测协处理器。它可以在 VA 发生前至少 15 美元预测 VA,准确率高达 91.6%。用于心律失常预测的协处理器架构(CoAP)使用从心电图信号中提取的最佳特征向量和优化的 DNN,并使用新型近似乘法器(AM)。CoAP 的工作频率为 12.5 kHz,采用 SCL 180 美元/文{-nm}$ 体 CMOS 技术实现时的功耗为 4.69 美元/文{W}$。与众所周知的最先进方法相比,拟议设计的低功耗实现及其更高的精度使其适用于可穿戴设备。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信