A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals — Comparison With Analog Version

Miguel Lima Teixeira;João P. Oliveira;José C. Príncipe;João Goes
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Abstract

Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 $\boldsymbol{\mu}$ W and 53 $\boldsymbol{\mu}$ W, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.
用于生物和低频信号的基于标准细胞的神经启发式集成与发射模-时转换器--与模拟版本的比较。
连续时间异步数据转换器,即模数转换器和模时转换器,可用于某些类型的应用,如处理信息稀疏的生物信号。这些转换器中的一个特殊例子就是受神经系统启发而产生的积分-发射转换器(IFC)。如果有可能开发出一种基于标准单元(SCB)的 IFC 电路,使其在先进技术节点中性能良好,那么它将受益于 SCB 电路设计的简便性,并可在广泛使用的现场可编程门阵列(FPGA)中实现。因此,本文提出了两个在 130 纳米 CMOS 标准工艺中设计和原型开发的 IFC 电路。第一个是新型 SCB 开环动态 IFC。后者是采用传统模块的闭环模拟 IFC。本文对这两种 IFC 电路进行了比较。SCB 和模拟 IFC 的功耗分别为 59 μW 和 53 μW,每个脉冲的能量分别为 18 pJ 和 1060 pJ。据报告,SCB IFC 是 IFC 电路中单位脉冲能耗最低的电路之一。据我们所知,全差分模拟 IFC 是同类电路中的首创。此外,它们不需要外部时钟。SCB 和模拟 IFC 的峰峰值幅度分别为 1.6 mV 至 28 mV 和 0.6 mV 至 2.4 mV,频率范围分别为 2 Hz 至 42 kHz 和 10 Hz 至 4 kHz。归一化有效值转换和重建误差较低,低于 5.2%。SCB 和模拟 IFC 的最大脉冲密度(平均发射率)分别为 3300 kHz 和 50 kHz。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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