A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance
IF 2.8 2区 工程技术Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
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引用次数: 0
Abstract
Hyperspectral and multispectral imaging maintains a crucial role in remote sensing technology for Earth observation missions. However, the huge volume of produced data requires compression for storage and downlink transmission. In 2019, the Consultative Committee for Space Data Systems (CCSDS) released the CCSDS 123.0-B-2 recommended standard, allowing near-lossless compression, through a closed-loop quantizer, by introducing a Hybrid Entropy Coder option. However, the in-loop quantizer introduced additional data dependencies constituting a throughput performance bottleneck. This contribution addresses the need for high data-rate on-board compression by presenting an efficient parallel architecture and hardware implementation based on CCSDS 123.0-B-2. It bypasses the throughput performance bottleneck with an external, hardware-efficient quantizer while maintaining competitive quality near-lossless functionality with compatibility to the CCSDS standard. The parallel architecture leverages segmentation along the X-axis of the spectral cube, enabling scalable data-rate performance with constant embedded memory footprint. The introduced architecture is implemented in VHSIC hardware description language (VHDL) indicatively targeting Xilinx Kintex UltraScale technology, validated and demonstrated using state-of-the-art SpaceFibre serial link interface IP Cores and test equipment, achieving very high code coverage. A single hyperspectral compression engine (HCE) achieves throughput performance of 285 MSamples/s (4.56 Gb/s) at 1.68 W, while six parallel HCEs reach 1590 MSamples/s (25.44 Gb/s) at 6.12 W, measured on a full breadboard system. Maximum performance only depends on image dimensions, available field programmable gate array (FPGA) resources and high-speed serial interface technology. To the best of our knowledge, this implementation achieves the highest data-rate performance for near-lossless compression based on CCSDS 123.0-B-2 implemented in FPGA technology suitable for next-generation institutional missions.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
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