A Parallel Architecture and Implementation for Near-Lossless Hyperspectral Image Compression Based on CCSDS 123.0-B-2 With Scalable Data-Rate Performance

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-26 DOI:10.1109/TVLSI.2024.3415505

Panagiotis Chatziantoniou;Antonis Tsigkanos;Dimitris Theodoropoulos;Nektarios Kranitis;Antonis Paschalis

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引用次数: 0

Abstract

Hyperspectral and multispectral imaging maintains a crucial role in remote sensing technology for Earth observation missions. However, the huge volume of produced data requires compression for storage and downlink transmission. In 2019, the Consultative Committee for Space Data Systems (CCSDS) released the CCSDS 123.0-B-2 recommended standard, allowing near-lossless compression, through a closed-loop quantizer, by introducing a Hybrid Entropy Coder option. However, the in-loop quantizer introduced additional data dependencies constituting a throughput performance bottleneck. This contribution addresses the need for high data-rate on-board compression by presenting an efficient parallel architecture and hardware implementation based on CCSDS 123.0-B-2. It bypasses the throughput performance bottleneck with an external, hardware-efficient quantizer while maintaining competitive quality near-lossless functionality with compatibility to the CCSDS standard. The parallel architecture leverages segmentation along the X-axis of the spectral cube, enabling scalable data-rate performance with constant embedded memory footprint. The introduced architecture is implemented in VHSIC hardware description language (VHDL) indicatively targeting Xilinx Kintex UltraScale technology, validated and demonstrated using state-of-the-art SpaceFibre serial link interface IP Cores and test equipment, achieving very high code coverage. A single hyperspectral compression engine (HCE) achieves throughput performance of 285 MSamples/s (4.56 Gb/s) at 1.68 W, while six parallel HCEs reach 1590 MSamples/s (25.44 Gb/s) at 6.12 W, measured on a full breadboard system. Maximum performance only depends on image dimensions, available field programmable gate array (FPGA) resources and high-speed serial interface technology. To the best of our knowledge, this implementation achieves the highest data-rate performance for near-lossless compression based on CCSDS 123.0-B-2 implemented in FPGA technology suitable for next-generation institutional missions.

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基于 CCSDS 123.0-B-2 的近乎无损高光谱图像压缩并行架构与实现，具有可扩展的数据速率性能

高光谱和多光谱成像技术在地球观测任务的遥感技术中发挥着至关重要的作用。然而，产生的大量数据需要压缩后才能存储和下行传输。2019 年，空间数据系统协商委员会（CCSDS）发布了 CCSDS 123.0-B-2 推荐标准，通过引入混合熵编码器选项，允许通过闭环量化器进行近乎无损的压缩。然而，内环量化器引入了额外的数据依赖性，构成了吞吐量性能瓶颈。本文提出了一种基于 CCSDS 123.0-B-2 的高效并行架构和硬件实现方法，以满足高数据率机载压缩的需求。它利用外部硬件高效量化器绕过了吞吐量性能瓶颈，同时保持了与 CCSDS 标准兼容的近乎无损的功能，质量极具竞争力。并行架构利用沿光谱立方体 X 轴的分段，实现了可扩展的数据速率性能和恒定的嵌入式内存占用空间。引入的架构采用 VHSIC 硬件描述语言（VHDL）实现，以 Xilinx Kintex UltraScale 技术为目标，使用最先进的 SpaceFibre 串行链路接口 IP 核和测试设备进行验证和演示，实现了极高的代码覆盖率。在全面包板系统上测量，单个高光谱压缩引擎（HCE）在 1.68 W 的功率下实现了 285 MS 样本/秒（4.56 Gb/秒）的吞吐量性能，而六个并行 HCE 在 6.12 W 的功率下实现了 1590 MS 样本/秒（25.44 Gb/秒）的吞吐量性能。最高性能仅取决于图像尺寸、可用的现场可编程门阵列 (FPGA) 资源和高速串行接口技术。据我们所知，这一实现达到了基于 CCSDS 123.0-B-2 的近乎无损压缩的最高数据速率性能，并采用了适合下一代机构任务的 FPGA 技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.