An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation

IF 2.8 2区 工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Jie Yuan
{"title":"An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation","authors":"Qifeng Huang;Siji Huang;Yanhang Chen;Yifei Fan;Jie Yuan","doi":"10.1109/TVLSI.2024.3417015","DOIUrl":null,"url":null,"abstract":"This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes \n<inline-formula> <tex-math>$689~\\mu $ </tex-math></inline-formula>\nW from a 1.8-V supply, achieving an FoM of -242.5 dB.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10571831/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

This article presents an injection-locked clock multiplier (ILCM) using a digitally controlled frequency-tracking loop (FTL) with an integral two-step switched-capacitor (SC) digital-to-analog converter (DAC). Conventionally, the DAC resolution needs to be increased for low noise at the cost of degraded monotonicity due to device mismatch. To overcome this tradeoff, the proposed DAC utilizes the SC technique to achieve fine steps. With only two capacitors involved in charge transfer, the DAC is inherently monotonic, avoiding the boundary-crossing issue and the mismatch calibration. A control-voltage-tracking loop (CVTL) further suppresses the quantization noise by balancing the up and down step sizes and helps achieve a 16-bit-level voltage step. The FTL is sub-sampling and utilizes a bang-bang phase detector (BBPD). Locking at 700 MHz, the ILCM achieves a 0.9-ps integrated jitter, a -125-dBc/Hz phase noise at a 1-MHz offset, and a small jitter variation of 2.67% under different supply voltages and temperatures. With FTL, the spur is around -56 dBc from the prototype fabricated in a 180-nm CMOS process. The chip occupies a core area of 0.054 mm2 and consumes $689~\mu $ W from a 1.8-V supply, achieving an FoM of -242.5 dB.
带有两级 SC DAC 的注入锁定和子采样时钟乘法器,抖动变化率为 2.67
本文介绍了一种注入锁定时钟乘法器(ILCM),该乘法器采用数字控制频率跟踪环路(FTL)和集成两步式开关电容(SC)数模转换器(DAC)。传统上,为了实现低噪声,需要提高 DAC 分辨率,但代价是器件失配导致单调性下降。为了克服这种折衷,所提出的 DAC 利用 SC 技术实现了精细阶跃。由于只有两个电容器参与电荷转移,因此 DAC 本身具有单调性,避免了越界问题和失配校准。控制电压跟踪环路 (CVTL) 通过平衡上下阶跃大小进一步抑制量化噪声,并有助于实现 16 位电平的电压阶跃。FTL 采用子采样,并使用了砰砰相位检测器 (BBPD)。ILCM 锁定频率为 700 MHz,综合抖动为 0.9ps,1 MHz 偏移时的相位噪声为 -125-dBc/Hz,在不同电源电压和温度条件下的抖动变化很小,仅为 2.67%。采用 180 纳米 CMOS 工艺制造的原型芯片,在 FTL 的情况下,抖动约为 -56 dBc。芯片核心面积为 0.054 mm2,1.8 V 电源功耗为 689~mu $ W,FoM 达到 -242.5 dB。
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来源期刊
CiteScore
6.40
自引率
7.10%
发文量
187
审稿时长
3.6 months
期刊介绍: The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.
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