Area Efficient 0.009-mm2 28.1-ppm/°C 11.3-MHz ALL-MOS Relaxation Oscillator

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-06-27 DOI:10.1109/TVLSI.2024.3416992

Joshua Adiel Wijaya;Poki Chen;Lucky Kumar Pradhan;Ahmad Shahid Bhatti;Seiji Kajihara

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引用次数: 0

Abstract

This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to replace the real resistor for efficient temperature compensation, which counterbalances the inherent proportional to absolute temperature (PTAT) property of the original relaxation circuit of the oscillator. The conventional capacitor is also replaced with a MOS capacitor to complete the ALL-MOS oscillator circuit with two prime advantages, one of which is larger capacitance to area density, and the other is better matching with critical MOSFETs. Implemented in a 0.18-

$\mu $

m TSMC standard CMOS process, the proposed relaxation oscillator has achieved a temperature coefficient of 28.17 ppm/°C over the temperature range from

$- 25~^{\circ }$

C to

$+ 125~^{\circ }$

C at 11.39-MHz oscillation frequency. This circuit consumes

$243.1~\mu $

W under 1.3-V power supply. Along with the abovementioned excellent performance, the oscillator achieves an ultrasmall core chip area of 0.009 mm2, which is almost one order less than most of the prior arts’ in the same process.

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面积效率 0.009-mm$^{2}$ 28.1-ppm/$^{circ}$C 11.3-MHz ALL-MOS 驰豫振荡器

本文介绍了一种具有低温灵敏度的超小面积片上弛豫振荡器。在这一设计中，实现了一个主要由绝对温度互补（CTAT）电压基准电路组成的虚拟电阻器，以取代实际电阻器，从而实现有效的温度补偿，抵消了振荡器原始弛豫电路固有的绝对温度成正比（PTAT）特性。此外，还用 MOS 电容器取代了传统的电容器，使全 MOS 振荡器电路具备了两个主要优势，其一是电容与面积密度更大，其二是与临界 MOSFET 的匹配性更好。在 0.18- $\mu $ m TSMC 标准 CMOS 工艺中实现的弛豫振荡器，在 11.39-MHz 振荡频率下，温度系数在 $- 25~^{\circ }$ C 到 $+ 125~^{\circ }$ C 的温度范围内达到了 28.17 ppm/°C。该电路在 1.3 V 电源下的功耗为 243.1~\mu $ W。除上述卓越性能外，该振荡器还实现了 0.009 mm2 的超小型核心芯片面积，比相同工艺下的大多数现有技术少了近一个数量级。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.