{"title":"A μ-GA Oriented ANN-Driven: Parameter Extraction of 5G CMOS Power Amplifier","authors":"Tahesin Samira Delwar;Abrar Siddique;Unal Aras;Yangwon Lee;Jee Youl Ryu","doi":"10.1109/TVLSI.2024.3414584","DOIUrl":null,"url":null,"abstract":"This article introduces a novel method for extracting crucial parameters from a fifth-generation (5G) CMOS power amplifier (PA) operating at 24 GHz. The proposed method, micro-genetic algorithm artificial neural network (\n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN), presents an innovative synergy between \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GA and ANN, enabling the accurate determination of crucial PA (circuit components) parameters. The \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN model has a fixed and robust stimulation function (\n<inline-formula> <tex-math>${F} {_{\\text {SF}}}$ </tex-math></inline-formula>\n and \n<inline-formula> <tex-math>${R} {_{\\text {SF}}}$ </tex-math></inline-formula>\n). ANNs are trained to approximate the parameter extraction process based on input-output data generated from the \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GA. The proposed \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GA incorporates the arithmetic crossover and nonuniform mutation; thus, several parameters of the ANN network are tweaked. Moreover, ANN parameters are enhanced by using \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GA to achieve an optimal PA design in a shorter period of time. To verify the proposed \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN, we have also compared the training time with particle swarm optimization (PSO) employed in ANN, i.e., PSOANN. Besides, a derivative superposition (DS) linearization technique is used in the PA circuit, along with input load splits (I-LSs) to solve the low input impedance problem of conventional DS. To design a PA, the proposed \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN outperforms the traditional feedforward artificial neural networks (TFFANN). Using \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN, the PA’s simulated S21 is 25 dB, while the measured S21 is 21.2 dB. With traditional TFFANN, we observe a simulated gain of 24.1 dB for the PA. We achieved a simulated gain of 23.2 dB of the PA without using ANNs. The measured results of the \n<inline-formula> <tex-math>$P {_{\\text {sat}}}$ </tex-math></inline-formula>\n and PAE of the PA with \n<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>\n-GAANN are 9.8 dBm and 32.1%, respectively. Also, a measured PA achieves a high third-order-input-intercept point (IIP3) of 14.1 dBm. The core chip area of the PA is 0.35 mm2.","PeriodicalId":13425,"journal":{"name":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","volume":null,"pages":null},"PeriodicalIF":2.8000,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10582892/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This article introduces a novel method for extracting crucial parameters from a fifth-generation (5G) CMOS power amplifier (PA) operating at 24 GHz. The proposed method, micro-genetic algorithm artificial neural network (
$\mu $
-GAANN), presents an innovative synergy between
$\mu $
-GA and ANN, enabling the accurate determination of crucial PA (circuit components) parameters. The
$\mu $
-GAANN model has a fixed and robust stimulation function (
${F} {_{\text {SF}}}$
and
${R} {_{\text {SF}}}$
). ANNs are trained to approximate the parameter extraction process based on input-output data generated from the
$\mu $
-GA. The proposed
$\mu $
-GA incorporates the arithmetic crossover and nonuniform mutation; thus, several parameters of the ANN network are tweaked. Moreover, ANN parameters are enhanced by using
$\mu $
-GA to achieve an optimal PA design in a shorter period of time. To verify the proposed
$\mu $
-GAANN, we have also compared the training time with particle swarm optimization (PSO) employed in ANN, i.e., PSOANN. Besides, a derivative superposition (DS) linearization technique is used in the PA circuit, along with input load splits (I-LSs) to solve the low input impedance problem of conventional DS. To design a PA, the proposed
$\mu $
-GAANN outperforms the traditional feedforward artificial neural networks (TFFANN). Using
$\mu $
-GAANN, the PA’s simulated S21 is 25 dB, while the measured S21 is 21.2 dB. With traditional TFFANN, we observe a simulated gain of 24.1 dB for the PA. We achieved a simulated gain of 23.2 dB of the PA without using ANNs. The measured results of the
$P {_{\text {sat}}}$
and PAE of the PA with
$\mu $
-GAANN are 9.8 dBm and 32.1%, respectively. Also, a measured PA achieves a high third-order-input-intercept point (IIP3) of 14.1 dBm. The core chip area of the PA is 0.35 mm2.
期刊介绍:
The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society.
Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels.
To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.