FPGA-enhanced system-on-chip for finger vein-based biometric system using novel DL model

Abstract

In an era dominated by technology, the imperative for robust personal authentication in electronic information systems becomes increasingly evident. A secure and dependable solution to address this need is biometric authentication. Due to their intrinsic features of being universal, unique, and fraud-resistant, finger vein-based recognition systems have gained importance. Veins provide an efficient barrier against misleading methods since they are buried under the skin and undetectable to human sight. While many researchers focus on advanced technology for finger-vein-based authentication systems, existing research has often overlooked significant challenges, such as short datasets, high computational complexity, and a lack of efficient and lightweight feature descriptors. This paper proposes a unique method for automated Finger Vein Recognition (FVR) based on a fusion model known as “CNN-ViT” for FVR. Transfer learning-based Convolutional Neural Network (CNN) models, such as Inception-V3 and ResNet-50, compute the correlation of adjacent pixels to process texture-based features. Furthermore, shape-based features are processed using the vision transformer (ViT) model to determine the relationship between distant pixels. The combination of these three models enables the learning of textural features based on forms, contributing to more effective finger vein identification. In addition to our databases, we utilize two benchmark databases, FV-USM and SDUMLA-HMT, to validate our experiments. Our proposed approach achieves outstanding accuracy values of 99.95 %, 98.9 %, and 97.78 % on both the benchmark and our datasets. When compared to previous methods, the proposed Deep Learning (DL) model outperforms state-of-the-art models, demonstrating higher recognition rates and accuracy. To prototype the proposed FVR system, a Zynq XCZU4EV UltraScale + Multiprocessor System-On-Chip (MPSoC) was employed. The proposed model exhibits high throughput and competitive power efficiency, making it an excellent choice for scenarios where computing performance is critical, albeit utilizing more power and resources. This was established through a comprehensive examination of FPGA resource utilization and performance metrics.