2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues

IF 2.2 3区工程技术 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

Integration-The Vlsi Journal Pub Date : 2024-06-14 DOI:10.1016/j.vlsi.2024.102230

Dharmaray Nedalgi , Saroja V. Siddamal , S.S. Kerur

引用次数: 0

Abstract

This paper presents circuit for $2 \times VDD$ signaling I/O buffer to solve the gate-oxide and hot-carrier reliability issues without consuming any active static power. The design is verified for a range of loads varying from 4 pF to 200 pF with operating speed ranging from 12 Mbps to 500 Mbps. The proposed circuit is implemented in 16 nm FinFET technology using 1.8 V thick gate devices. The design can be used in any CMOS technology for $2 \times VDD$ signaling I/O buffer to reduce hot-carrier effect and to avoid gate-oxide reliability issues.

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2×VDD IO 缓冲器，带有本文介绍了 2×VDD 信号 I/O 缓冲器电路，以解决栅极氧化和热载波可靠性问题，而无需消耗任何有源静态功率。该设计在 4 pF 至 200 pF 的负载范围内进行了验证，工作速度为 12 Mbps 至 500 Mbps。该电路采用 16 纳米 FinFET 技术，使用 1.8 V 厚栅极器件实现。该设计可用于任何 CMOS 技术的 2×VDD 信号 I/O 缓冲器，以减少热载波效应，避免栅极氧化物的可靠性问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Integration-The Vlsi Journal 工程技术-工程：电子与电气

CiteScore

3.80

自引率

5.30%

发文量

107

审稿时长

6 months

期刊介绍： Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics: Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.