High-Energy Dynamic Avalanche to Failure by Incremental Source-Voltage Increase in Symmetric Double-Trench & Asymmetric Trench SiC MOSFETs

Abstract

The unclamped inductive switching (UIS) measurements can be categorized as “low energy” and “high energy” avalanche. The conventional approach to these tests is to increase the stress by either increasing the pulse length, or decreasing the inductor's size. However, for evaluation of the novel trench SiC mosfet s, increase of electric field by voltage can be more influential to detect the degradation patterns and exact point of failure. This article, for the first time, investigates the avalanche rating to failure of the similarly rated SiC power mosfet s in planar, symmetric double-trench and asymmetrical trench structures through incremental increase of applied voltage as the “high energy” technique to investigate the mechanisms of dynamic avalanche under elevated electric fields. Using this approach, the electrothermal stress is induced by incremental increases of voltage source on UIS at a range of temperatures between 25 °C and 175 °C. Silvaco technology computer-aided design (TCAD) simulations have been developed, validated, and analyzed to evaluate the stress mechanisms to failure. The measurements, validated by TCAD, show that some failure mechanisms when stress is elevated by increase of source voltage are different than the case of “high current” avalanche initiation by increase of pulse durations as reported in the past. In planar device, the peak electric field plays a key role in failure, as is the failure in symmetric device at low case temperatures. In asymmetric device, the critical avalanche energy of failure in both cases of 25 °C and 175 °C are very close, suggesting independence from the thermal headroom.