{"title":"A 60-GHz Phase-Locked Loop Using Standing- Wave Oscillator for Clock Distribution in 2-D Phased-Array","authors":"Ying-Han You;Sih-Ying Chen;Pin-Yu Lin;Jun-Chau Chien","doi":"10.1109/LMWT.2024.3388933","DOIUrl":null,"url":null,"abstract":"This letter presents a 60-GHz analog phase-locked loop (PLL) incorporating a half-wavelength standing-wave oscillator (SWO) as part of the clock distribution network in a sub-THz 2-D phased-array transceiver. The frequency is selected as one-fourth of the target carrier frequency to comply with the 625-\n<inline-formula> <tex-math>$\\mu \\text{m}$ </tex-math></inline-formula>\n half- wavelength element spacing requirement while facilitating array scaling. The PLL features a sampler-based phase detector (PD) and retiming flip-flop at the divider chain output to ensure minimal noise injection. Fabricated in TSMC 28-nm CMOS, the measurement results show an integrated jitter of 87.5 fsec from 1 kHz to 100 MHz. Consuming 31.35 mW of power, the presented PLL achieves a figure-of-merit of -270 dB.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10507886/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This letter presents a 60-GHz analog phase-locked loop (PLL) incorporating a half-wavelength standing-wave oscillator (SWO) as part of the clock distribution network in a sub-THz 2-D phased-array transceiver. The frequency is selected as one-fourth of the target carrier frequency to comply with the 625-
$\mu \text{m}$
half- wavelength element spacing requirement while facilitating array scaling. The PLL features a sampler-based phase detector (PD) and retiming flip-flop at the divider chain output to ensure minimal noise injection. Fabricated in TSMC 28-nm CMOS, the measurement results show an integrated jitter of 87.5 fsec from 1 kHz to 100 MHz. Consuming 31.35 mW of power, the presented PLL achieves a figure-of-merit of -270 dB.