Joon-Hyung Kim;Han-Woong Choi;Min-Seok Baek;Choul-Young Kim
{"title":"180° Switching Method Based on Transformer for CMOS Phase Shifter","authors":"Joon-Hyung Kim;Han-Woong Choi;Min-Seok Baek;Choul-Young Kim","doi":"10.1109/LMWT.2024.3392986","DOIUrl":null,"url":null,"abstract":"A novel 180° switching method based on transformer for phase shifter (PS) is proposed. The proposed method provides low phase error (PE) and low gain error, which enhances the overall performance of the PS. To demonstrate the feasibility of the proposed circuit configuration, the PS is implemented using a 65-nm bulk complementary metal–oxide–semiconductor (CMOS) process. Using the proposed 180°-unit structure, a fully integrated PS with a resolution of 6 bits shows the rms PE of 2.4°–3.0° and the rms gain error of 0.8–1.0 dB with <−10> <tex-math>$S_{11}$ </tex-math></inline-formula>\n, \n<inline-formula> <tex-math>$S_{22}$ </tex-math></inline-formula>\n). The measured insertion loss is 9.3 dB at 24 GHz. The power dissipation of PS is zero and the core size is 0.18 mm2.","PeriodicalId":73297,"journal":{"name":"IEEE microwave and wireless technology letters","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE microwave and wireless technology letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10510444/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"0","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A novel 180° switching method based on transformer for phase shifter (PS) is proposed. The proposed method provides low phase error (PE) and low gain error, which enhances the overall performance of the PS. To demonstrate the feasibility of the proposed circuit configuration, the PS is implemented using a 65-nm bulk complementary metal–oxide–semiconductor (CMOS) process. Using the proposed 180°-unit structure, a fully integrated PS with a resolution of 6 bits shows the rms PE of 2.4°–3.0° and the rms gain error of 0.8–1.0 dB with <−10> $S_{11}$
,
$S_{22}$
). The measured insertion loss is 9.3 dB at 24 GHz. The power dissipation of PS is zero and the core size is 0.18 mm2.