A 1.11 mm2 IVUS SoC with ±50°-Range Plane Wave Transmit Beamforming at 40 MHz.

Xitie Zhang, Evren F Arkan, Coskun Tekes, M Sait Kilinc, Tzu-Han Wang, F Levent Degertekin, Shaolan Li
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Abstract

Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between ~0 and 10 ns in two directions, generating a steerable plane wave in a range of ±/-50° for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm × 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.

1.11 平方毫米 IVUS 系统芯片,采用 40 兆赫 ±50° 范围平面波发射波束成形技术。
血管内超声(IVUS)成像导管是心血管介入治疗的重要工具,通过实现 IVUS 成像导丝和微导管,可以扩大其使用范围。这些设备的微型化给信噪比带来了挑战,因为需要更高的频率才能提供足够的分辨率。具有发射波束成形功能的集成 IVUS 系统可减轻这些限制。这项研究提出了首个实用的高度集成的片上系统(SoC),该系统具有 40 MHz 的平面波发射波束成形功能,可用于导丝或微导管上的 IVUS。前端电路有 20 个通道的超声波发射器(Tx)和接收器(Rx)阵列,与电容式微机械超声波换能器(CMUT)阵列相连接。在每次发射过程中,所有 20 个 Tx 都以相对于彼此的相同模拟延迟进行激励,该延迟可在两个方向上在 ~0 至 10 ns 之间连续调整,从而在 40 MHz 的相控阵列中产生 ±/-50° 范围内的可转向平面波。单元延迟通过压控延迟线(VCDL)产生,只需两个外部控制,一个调整单元延迟,另一个确定转向方向。系统级芯片采用 180 纳米高压 (HV) CMOS 工艺制造,有效面积仅为 0.3 毫米 × 3.7 毫米。拟议的 SoC 在接收模式下的功耗为 31.3 mW。波束形成器的功能和 SoC 的整体性能通过声学表征和成像实验得到了验证。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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