DSCAM: Latency-Guaranteed and High-Capacity Content-Addressable Memory on FPGAs

IF 1.7 4区计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Embedded Systems Letters Pub Date : 2023-11-20 DOI:10.1109/LES.2023.3334288

Shervin Vakili;Amirhossein Zarei

引用次数: 0

Abstract

This letter introduces an original and highly efficient method to implement high-capacity content-addressable memories on field programmable gate arrays (FPGAs). The method includes a new hardware architecture and an optimization technique to determine crucial design parameters. The memory contents are partially synthesized and implemented on FPGA logic fabrics. The proposed architecture offers high throughput and fixed-latency searches. Experimental results show that the proposed method enables the implementation of an IPv4 forwarding table with over 520 K prefixes on a cost-effective AMD-Xilinx UltraScale + FPGA, providing a lookup latency of less than 28 ns and a minimum throughput of 215 million lookups per second. The source code of this work is available on GitHub.

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DSCAM：FPGA 上的延迟保证和大容量内容可寻址存储器

这封信介绍了一种在现场可编程门阵列（FPGA）上实现大容量内容可寻址存储器的高效独创方法。该方法包括一种新的硬件架构和一种用于确定关键设计参数的优化技术。存储器内容在 FPGA 逻辑结构上进行部分合成和实现。所提出的架构可提供高吞吐量和固定延迟搜索。实验结果表明，所提出的方法能够在高性价比的 AMD-Xilinx UltraScale + FPGA 上实现包含超过 520 K 个前缀的 IPv4 转发表，查询延迟小于 28 ns，最低吞吐量为每秒 2.15 亿次查询。这项工作的源代码可在 GitHub 上获取。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Embedded Systems Letters Engineering-Control and Systems Engineering

CiteScore

3.30

自引率

0.00%

发文量

期刊介绍： The IEEE Embedded Systems Letters (ESL), provides a forum for rapid dissemination of latest technical advances in embedded systems and related areas in embedded software. The emphasis is on models, methods, and tools that ensure secure, correct, efficient and robust design of embedded systems and their applications.