(Invited) Bulk Traps in Layered 2D Gate Dielectrics

Abstract

In this work, we synthesize new 2D layered dielectrics and fabricate metal-insulator-metal (MIM) capacitors to determine their viability for scaled gate dielectrics (ZrNCl, HfNCl, BiOCl, and Mg(OH)2) in transition metal dichalcogenide-based transistors. While successful synthesis and fabrication was demonstrated, the properties of the dielectrics were decidedly underwhelming for device applications. The dielectric constants, in most cases, were only marginally better than SiO2 (k = 4-6), the leakage currents were too high due to poor band offsets, and most importantly, the bulk trap density, as seen previously in III-V devices, was very high. Overall, there still is no viable 2D gate dielectric for scaled field effect transistors.