{"title":"Design of CMOS fully differential multipath two-stage OTA with boosted slew rate and power efficiency","authors":"Zahra Hashemi, Mostafa Yargholi","doi":"10.1016/j.vlsi.2024.102204","DOIUrl":null,"url":null,"abstract":"<div><p>A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.</p></div>","PeriodicalId":54973,"journal":{"name":"Integration-The Vlsi Journal","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Integration-The Vlsi Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167926024000683","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
A CMOS fully differential multipath two-stage operational transconductance amplifier (OTA) with boosted slew rate and power efficiency is proposed in this paper. The new OTA consists of two gain stages. The basic structure of the proposed OTA is the recycling folded cascode (RFC) structure. By using the multipath technique in the first stage of the proposed OTA, it leads to an increase in gain and a decrease in power consumption. In addition, a high-speed current mirror is applied to increase the phase margin. The second stage with a class-AB amplifier is used to increase the transconductance and slew rate of the output. Moreover, the power efficiency of the proposed OTA is boosted compared to the recycling double-folded cascode (RDFC) OTA. This makes the proposed OTA more appropriate for applications that require low power consumption, such as neural amplifiers. Design and simulation of the proposed OTA is done in 0.18 μm standard CMOS technology with a 1 V supply voltage. Post-layout simulation results of the proposed OTA demonstrate that the OTA dissipates 180 nW of power, while showing a 136.7 dB voltage gain, and 127.1 kHz unity gain frequency for a capacitive load of 30 pF. Thus, compared to the RDFC OTA, the proposed OTA provides a 250 % increase in slew rate and a 20 % increase in PSRR and CMRR, while power consumption is reduced by 10 %. The proposed OTA is robust against process, voltage, and temperature (PVT) variations. The recommended OTA achieves a good figure of merit (FOM) over the previous OTAs.
本文提出了一种具有更高转速和能效的 CMOS 全差分多路两级运算转导放大器(OTA)。新型 OTA 由两个增益级组成。拟议 OTA 的基本结构是循环折叠级联(RFC)结构。通过在第一级 OTA 中使用多路径技术,可提高增益并降低功耗。此外,还采用了高速电流镜来增加相位裕量。带有 AB 类放大器的第二级用于提高输出的跨导和压摆率。此外,与循环双折叠级联(RDFC)OTA 相比,拟议 OTA 的功率效率有所提高。这使得拟议的 OTA 更适合需要低功耗的应用,如神经放大器。拟议 OTA 的设计和仿真采用 0.18 μm 标准 CMOS 技术,电源电压为 1 V。拟议 OTA 的布局后仿真结果表明,该 OTA 的耗散功率为 180 nW,电压增益为 136.7 dB,在 30 pF 的电容负载条件下,单位增益频率为 127.1 kHz。因此,与 RDFC OTA 相比,拟议 OTA 的压摆率提高了 250%,PSRR 和 CMRR 提高了 20%,同时功耗降低了 10%。建议的 OTA 对工艺、电压和温度(PVT)变化具有鲁棒性。与之前的 OTA 相比,推荐的 OTA 实现了良好的性能指标(FOM)。
期刊介绍:
Integration''s aim is to cover every aspect of the VLSI area, with an emphasis on cross-fertilization between various fields of science, and the design, verification, test and applications of integrated circuits and systems, as well as closely related topics in process and device technologies. Individual issues will feature peer-reviewed tutorials and articles as well as reviews of recent publications. The intended coverage of the journal can be assessed by examining the following (non-exclusive) list of topics:
Specification methods and languages; Analog/Digital Integrated Circuits and Systems; VLSI architectures; Algorithms, methods and tools for modeling, simulation, synthesis and verification of integrated circuits and systems of any complexity; Embedded systems; High-level synthesis for VLSI systems; Logic synthesis and finite automata; Testing, design-for-test and test generation algorithms; Physical design; Formal verification; Algorithms implemented in VLSI systems; Systems engineering; Heterogeneous systems.