A Power-and-Area-Efficient Channel-Interleaved Neural Signal Processor for Wireless Brain-Computer Interfaces with Unsupervised Spike Sorting.

Abstract

Next generation of wireless brain-computer-interface (BCI) devices require dedicated neural signal processors (NSPs) to extract key neurological information while operating within given power consumption and transmission bandwidth limits. Spike detection and clustering are important signal processing steps in neurological research and clinical applications. Computational-friendly spike detection and feature extraction algorithms are first systematically evaluated in this work. The nonlinear energy operator (NEO) and the first-and-second-derivative (FSDE) together with the 'perturbed' K-mean clustering achieve the highest accuracy performance. An NSP ASIC is implemented in a channel-interleaved architecture and the folding ratio of 16 leads to the minimum power-and-area product. As the result, the NSP consumes 2-μW power consumption and occupies 0.0057 mm2 for each channel in a 65-nm CMOS technology. The proposed system achieves the unsupervised spike classification accuracy of 92% and a data-rate reduction of 98.3%, showing the promise for realizing high-channel-count wireless BCIs.