An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-04-29 DOI:10.1109/TVLSI.2024.3392611

Siji Huang;Debajit Basak;Yanhang Chen;Qifeng Huang;Yifei Fan;Jie Yuan

引用次数: 0

Abstract

This article presents a timing-skew-free time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC). By implementing an architecture with a single sample-and-hold (S/H) network, this design eliminates the need for a costly timing-skew calibration. Additionally, compared to architectures that utilize multiple S/H networks, it offers hardware and power savings. As a result, the proposed design is efficient in terms of energy and area, making it suitable for applications that require multiple ADC channels. A prototype ADC is designed and fabricated in a 28-nm CMOS process. The TI SAR ADC, running at 1.4 GS/s, achieves a signal-to-noise-and-distortion ratio (SNDR) and spurious free dynamic range (SFDR) of 48.1 and 58.4 dB with a Nyquist input, respectively. It dissipates 24 mW, leading to a Walden figure-of-merit (FoM) of 82.4 fJ/conv.-step. The chip occupies an active area of 0.06 mm2.

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具有集中采样前端的高效 1.4-GS/s 10 位无定时偏移时交织 SAR ADC

本文介绍了一种无时序偏移的逐次逼近寄存器（TI）模数转换器（ADC）。通过采用具有单一采样和保持（S/H）网络的架构，该设计无需进行昂贵的时序偏差校准。此外，与使用多个 S/H 网络的架构相比，它还能节省硬件和功耗。因此，所提出的设计在能耗和面积方面都很高效，适用于需要多个 ADC 通道的应用。采用 28 纳米 CMOS 工艺设计并制造了一个 ADC 原型。TI SAR ADC 的运行速度为 1.4 GS/s，在奈奎斯特输入下的信噪比 (SNDR) 和无杂散动态范围 (SFDR) 分别达到 48.1 和 58.4 dB。它的功耗为 24 mW，沃顿功耗系数（FoM）为 82.4 fJ/conv.-step。芯片的有效面积为 0.06 平方毫米。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

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