Symmetric and Multiphase-Interleaved Ladder Bucks for DC Capacitors Elimination

IF 2.8 2区工程技术 Q2 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Pub Date : 2024-04-29 DOI:10.1109/TVLSI.2024.3392617

Loai G. Salem

引用次数: 0

Abstract

To improve power density, a symmetric switched-capacitor (SC) ladder buck (SLB) is proposed in this brief that eliminates the fixed ladder in an SC ladder buck (SCLB) by tying the dc nodes in two 180°-phase-shifted cells together. Unlike flying capacitor multilevel converters (FCMCs) that minimize the inductor current ripple, the ladder topology within an SCLB splits the inductor current optimally among the ladder switches, such that the overall equivalent output resistance is minimized. M-phase interleaving is proposed in this brief to allow SLB to regain this current splitting capability when operating via duty cycles larger than 0.5. Simulation results of a six-level four-phase design in 180-nm CMOS verify the performance advantages of the proposed topology.

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用于消除直流电容的对称和多相交错梯形降压器

为了提高功率密度，本简介提出了一种对称开关电容器（SC）梯形降压（SLB），通过将两个 180° 相移单元中的直流节点绑在一起，消除了 SC 梯形降压（SCLB）中的固定梯形。与最大限度降低电感器电流纹波的飞电容多电平转换器（FCMC）不同，SCLB 中的梯形拓扑结构可在梯形开关之间最佳地分配电感器电流，从而最大限度地降低整体等效输出电阻。本简介中提出的 M 相交错技术可让 SLB 在占空比大于 0.5 的情况下重新获得这种电流分流能力。180 纳米 CMOS 六级四相设计的仿真结果验证了所提拓扑结构的性能优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Transactions on Very Large Scale Integration (VLSI) Systems 工程技术-工程：电子与电气

CiteScore

6.40

自引率

7.10%

发文量

187

审稿时长

3.6 months

期刊介绍： The IEEE Transactions on VLSI Systems is published as a monthly journal under the co-sponsorship of the IEEE Circuits and Systems Society, the IEEE Computer Society, and the IEEE Solid-State Circuits Society. Design and realization of microelectronic systems using VLSI/ULSI technologies require close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing and systems applications. Generation of specifications, design and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems have been founded. The editorial board, consisting of international experts, invites original papers which emphasize and merit the novel systems integration aspects of microelectronic systems including interactions among systems design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and systems level qualification. Thus, the coverage of these Transactions will focus on VLSI/ULSI microelectronic systems integration.

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