SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule

Abstract

The brain's ability to anticipate future events is crucial for intelligent behavior. However, when deploying the capability to edge devices, there are huge challenges in terms of resources and power consumption. The main obstacle is the state-of-the-art neuromorphic hardware with Spike Timing Dependent Plasticity (STDP) learning rule requires significant computation for synaptic weight updates and memory to store intermediate synaptic weights. In this paper, we proposed an approximate Spiking Neural Network (SNN) accelerator with on-chip Predictive Learning Rule (PLR), which is a biological behavior observed in the brain, named SC-PLR. In SC-PLR, the principles of predictive processing are extended to enable neurons to learn temporal sequences and anticipate future events with minimum synaptic weight updates, while stochastic computing is leveraged to balance the hardware cost, energy efficiency, and accuracy. Simulation results demonstrate that PLR-based SNNs effectively enable adaptive and anticipatory behavior in robotics and decision-making scenarios. Additionally, FPGA implementation results show that the proposed SC-PLR outperforms state-of-the-art STDP-based SNN designs in terms of resources and power consumption. Specifically, our design achieves significant resource savings, including 77.3% Look-Up Table (LUT), 79.4% Flip-Flop (FF), and 56.4% Block RAM (BRAM) resources, and power consumption reduction by 32%. ^{1 1}

The code is available at https://github.com/lucy-weizi/SC-PLR.