FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-11-28 DOI:10.1109/LCA.2023.3336841

Hyeseong Kim;Yunjae Lee;Minsoo Rhu

引用次数: 0

Abstract

Deep neural network (DNN)-based recommendation systems (RecSys) are one of the most successfully deployed machine learning applications in commercial services for predicting ad click-through rates or rankings. While numerous prior work explored hardware and software solutions to reduce the training time of RecSys, its end-to-end training pipeline including the data preprocessing stage has received little attention. In this work, we provide a comprehensive analysis of RecSys data preprocessing, root-causing the feature generation and normalization steps to cause a major performance bottleneck. Based on our characterization, we explore the efficacy of an FPGA-accelerated RecSys preprocessing system that achieves a significant 3.4–12.1× end-to-end speedup compared to the baseline CPU-based RecSys preprocessing system.

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用于个性化推荐系统的 FPGA 加速数据预处理

基于深度神经网络（DNN）的推荐系统（RecSys）是商业服务中最成功的机器学习应用之一，用于预测广告点击率或排名。虽然之前有大量工作探索了缩短 RecSys 训练时间的硬件和软件解决方案，但包括数据预处理阶段在内的端到端训练流水线却很少受到关注。在这项工作中，我们对 RecSys 的数据预处理进行了全面分析，从根本上找出了导致主要性能瓶颈的特征生成和归一化步骤。基于我们的分析，我们探索了 FPGA 加速 RecSys 预处理系统的功效，与基于 CPU 的基线 RecSys 预处理系统相比，该系统的端到端速度显著提高了 3.4-12.1 倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.