Design and analysis of sum-prediction adder

Abstract

It is well known that addition is an essential arithmetic operation in multi-medium applications, wireless applications and multiplication. Based on the predictable sum bits in the addition of two n-bit integers, the logical circuit of an n-bit sum-prediction adder can be constructed and the hardware overhead and the static timing delay of the proposed n-bit sum-prediction adder can be analyzed. In the design of an n-bit sum-prediction adder, the predictable carry bits can lead to the generation of the predictable sum bits in the addition of two n-bit integers. Based on the generation of the predictable sum bits, the carry propagation on a longer link of NMOS transistors can be separated into some carry propagation on some shorter links and the unknown sum bits can be divided into some sum blocks. Furthermore, the unknown sum bits inside each sum block can be generated by propagating the predicted sum bits. For the comparison of the average power and the timing delay in 90 nm technology on the RCAs using full adders, 2-bit CLA blocks, 4-bit CLA blocks, 1-bit CSA blocks, 2-bit CSA blocks or 4-bit CSA blocks, the proposed sum-prediction adder can reduce 5.9 %, 30.7 %, 45.0 %, 18.1 %, 18.8 % and 19.0 % of the average power and reduce 35.0 %, 41.4 %, 12.5 %, 72.3 %, 67.1 % and 62.7 % of the timing delay on the average, respectively.