General Fault and Soft-Error Tolerant Phase-Locked Loop by Enhanced TMR using A Synchronization-before-Voting Scheme

Abstract

A Phase-Locked Loop (PLL) is indispensable in producing high-speed on-chip clock signals in an IC. For safety–critical applications, fault and soft-error tolerance are often desirable. However, how to achieve this goal for a PLL is still a challenge. In this paper, we address this challenge with a TMR-based FET-PLL design. Our unique contribution is a “synchronization-before-voting” scheme so that the fault and soft-error tolerance and the jitter performance can be maintained at the same time. Post-layout simulation using a 90 nm CMOS process demonstrates that our PLL can indeed withstand the attack of online faults as well as soft errors without suffering from significant jitter performance loss.