DRAMA: Commodity DRAM Based Content Addressable Memory

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-12-12 DOI:10.1109/LCA.2023.3341830

L. Yavits

引用次数: 0

Abstract

Fast parallel search capabilities on large datasets provided by content addressable memories (CAM) are required across multiple application domains. However compared to RAM, CAMs feature high area overhead and power consumption, and as a result, they scale poorly. The proposed solution, DRAMA, enables CAM, ternary CAM (TCAM) and approximate (similarity) search CAM functionalities in unmodified commodity DRAM. DRAMA performs compare operation in a bit-serial fashion, where the search pattern (query) is coded in DRAM addresses. A single bit compare (XNOR) in DRAMA is identical to a regular DRAM read. AND and OR operations required for NAND CAM and NOR CAM respectively are implemented using nonstandard DRAM timing. We evaluate DRAMA on bacterial DNA classification and show that DRAMA can achieve 3.6

$ \times $

higher performance and 19.6

$ \times $

lower power consumption compared to state-of-the-art CMOS CAM based genome classification accelerator.

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DRAMA：基于商品 DRAM 的内容可寻址存储器

多个应用领域都需要内容可寻址存储器（CAM）在大型数据集上提供快速并行搜索功能。然而，与 RAM 相比，CAM 的面积开销大、功耗高，因此扩展性较差。所提出的 DRAMA 解决方案可在未修改的商品 DRAM 中实现 CAM、三元 CAM (TCAM) 和近似（相似性）搜索 CAM 功能。DRAMA 以位串行方式执行比较操作，其中搜索模式（查询）以 DRAM 地址编码。DRAMA 中的单比特比较 (XNOR) 与常规 DRAM 读取相同。NAND CAM 和 NOR CAM 所需的 AND 和 OR 运算分别使用非标准 DRAM 时序实现。我们对 DRAMA 进行了细菌 DNA 分类评估，结果表明，与基于 CMOS CAM 的最先进基因组分类加速器相比，DRAMA 的性能提高了 3.6 倍，功耗降低了 19.6 倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.