A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier

Abstract

The paper proposes a novel 3 × 3 reversible gate which has varied functionality for logical and arithmetic operations. The advancements in VLSI demand higher operational speed and less time delay, which leads to increased complexity and more power dissipation in the design. The continuous evolution of DSP applications demands improvisation on the multiplier design that is faster and more power efficient. Reversible logic is an efficient solution to the above problems. In the paper, a basic 2 × 2 multiplier, the proposed novel gate, and its enhanced capability for implementing half adder-subtractor over existing basic reversible gates are discussed. The proposed designs were implemented on QCA Designer.