{"title":"Simultaneous Characterization of Both Ctes and Thermal Warpages of Flip-Chip Packages with a Cap Using Strain Gauges","authors":"Yu Wen Wang, M. Tsai, Y. S. Chou","doi":"10.1115/1.4064354","DOIUrl":null,"url":null,"abstract":"\n A relatively low-cost and easy-to-use strain gauge measurement is proposed here as an alternative method for simultaneously determining the thermally-induced warpages and the coefficients of thermal expansion (CTEs) of the flip-chip packages with a cap (or lid). The feasibility of the strain gauge method is evaluated by the shadow moiré experiment and the finite element analysis. The stiffness effect of the thermal interface materials (TIMs) in the flip-chip packages with a cap is also considered. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM is relatively compliant, but not for stiff TIMs. This study also proposes a modified gauge method with a few related strain equations for those cases with compliant TIMs to effectively determine their thermal warpages and CTEs by the gauge measurement. The finite element method (FEM) simulation, consistent with shadow moiré, has further validated the effectiveness of the modified gauge method. Therefore, the newly developed and modified method of strain gauges is found to be feasible and workable for simultaneously determining both thermal warpages and CTEs of the flip-chip packages with a cap, especially with a compliant TIM.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"68 5","pages":""},"PeriodicalIF":2.2000,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electronic Packaging","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1115/1.4064354","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
A relatively low-cost and easy-to-use strain gauge measurement is proposed here as an alternative method for simultaneously determining the thermally-induced warpages and the coefficients of thermal expansion (CTEs) of the flip-chip packages with a cap (or lid). The feasibility of the strain gauge method is evaluated by the shadow moiré experiment and the finite element analysis. The stiffness effect of the thermal interface materials (TIMs) in the flip-chip packages with a cap is also considered. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM is relatively compliant, but not for stiff TIMs. This study also proposes a modified gauge method with a few related strain equations for those cases with compliant TIMs to effectively determine their thermal warpages and CTEs by the gauge measurement. The finite element method (FEM) simulation, consistent with shadow moiré, has further validated the effectiveness of the modified gauge method. Therefore, the newly developed and modified method of strain gauges is found to be feasible and workable for simultaneously determining both thermal warpages and CTEs of the flip-chip packages with a cap, especially with a compliant TIM.
本文提出了一种成本相对较低且易于使用的应变片测量方法,作为同时测定带盖倒装芯片封装的热致翘曲和热膨胀系数(CTE)的替代方法。通过阴影摩尔纹实验和有限元分析评估了应变计方法的可行性。此外,还考虑了带盖倒装芯片封装中热界面材料(TIM)的刚度效应。结果表明,在试样顶部和底部采用一般的背靠背量规测量方法会因 TIM 的相对顺从性而导致重大误差,但对于刚性 TIM 则不会。本研究还针对具有顺应性 TIM 的情况,提出了一种改进的量规测量方法,其中包含一些相关的应变方程,可通过量规测量有效确定其热翘曲和 CTE。与阴影摩尔相一致的有限元法(FEM)模拟进一步验证了修正量规法的有效性。因此,新开发和改进的应变片方法对于同时确定带盖倒装芯片封装(尤其是兼容 TIM)的热翘曲和 CTE 是可行的。
期刊介绍:
The Journal of Electronic Packaging publishes papers that use experimental and theoretical (analytical and computer-aided) methods, approaches, and techniques to address and solve various mechanical, materials, and reliability problems encountered in the analysis, design, manufacturing, testing, and operation of electronic and photonics components, devices, and systems.
Scope: Microsystems packaging; Systems integration; Flexible electronics; Materials with nano structures and in general small scale systems.