Cooperative engineering the multiple radio-frequency fields to reduce the X-junction barrier for ion trap chips

Chip Pub Date : 2024-03-01 DOI:10.1016/j.chip.2023.100078
Yarui Liu , Zhao Wang , Zixuan Xiang , Qikun Wang , Tianyang Hu , Xu Wang
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引用次数: 0

Abstract

With the increasing number of ion qubits and improving performance of sophisticated quantum algorithms, more and more scalable complex ion trap electrodes have been developed and integrated. Nonlinear ion shuttling operations at the junction are more frequently used, such as in the areas of separation, merging, and exchanging. Several studies have been conducted to optimize the geometries of the radio-frequency (RF) electrodes to generate ideal trapping electric fields with a lower junction barrier and an even ion height of the RF saddle points. However, this iteration is time-consuming and commonly accompanied by complicated and sharp electrode geometry. Therefore, high-accuracy fabrication process and high electric breakdown voltage are essential. In the current work, an effective method was proposed to reduce the junction's pseudo-potential barrier and ion height variation by setting several individual RF electrodes and adjusting each RF voltage amplitude without changing the geometry of the electrode structure. The simulation results show that this method shows the same effect on engineering the trapping potential and reducing the potential barrier, but requires fewer parameters and optimization time. By combining this method with the geometrical shape-optimizing, the pseudo-potential barrier and the ion height variation near the junction can be further reduced. In addition, the geometry of the electrodes can be simplified to relax the fabrication precision and keep the ability to engineer the trapping electric field in real-time even after the fabrication of the electrodes, which provides a potential all-electric degree of freedom for the design and control of the two-dimensional ion crystals and investigation of their phase transition.

合作设计多个射频场以降低离子阱芯片的 X 结障碍
随着离子量子比特和复杂量子算法的不断增加,人们开发并集成了更多可扩展的复杂离子阱电极。交界处的非线性离子穿梭操作被更频繁地使用,如分离、合并和交换。为了产生理想的俘获电场,同时降低结界屏障和射频鞍点的离子高度,已经开展了多项优化射频(RF)电极几何形状的研究。然而,这种反复试验非常耗时,而且通常伴随着复杂而尖锐的电极几何形状。在此,我们提出了一种有效的方法,即在不改变电极结构几何形状的前提下,通过设置多个单独的射频电极和调整每个射频电压幅值来降低结的伪电势势垒和离子高度变化。模拟结果表明,这种方法在设计捕获电位和降低电位势垒方面具有相同的效果,但所需的参数和优化时间更少。通过将这种方法与几何形状优化相结合,可以进一步降低结点附近的伪电势势垒和离子高度变化。此外,还可以简化电极的几何形状,放宽制造精度,即使在电极制造完成后也能保持实时设计捕获电场的能力,为设计和控制二维离子晶体以及研究其相变提供了潜在的全电自由度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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2.80
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