Redundant Array of Independent Memory Devices

IF 1.4 3区计算机科学 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Computer Architecture Letters Pub Date : 2023-11-20 DOI:10.1109/LCA.2023.3334989

Peiyun Wu;Trung Le;Zhichun Zhu;Zhao Zhang

引用次数: 0

Abstract

DRAM memory reliability is increasingly a concern as recent studies found. In this letter, we propose RAIMD (Redundant Array of Independent Memory Devices), an energy-efficient memory organization with RAID-like error protection. In this organization, each memory device works as an independent memory module to serve a whole memory request and to support error detection and error recovery. It relies on the high data rate of modern memory device to minimize the performance impact of increased data transfer time. RAIMD provides chip-level error protection similar to Chipkill but with significant energy savings. Our simulation results indicate that RAIMD can save memory energy by 26.3% on average with a small performance overhead of 5.3% on DDR5-4800 memory systems for SPEC2017 multi-core workloads.

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独立内存设备冗余阵列

最近的研究发现，DRAM存储器的可靠性越来越受到关注。在这封信中，我们提出RAIMD(独立存储器设备冗余阵列)，一种具有类似raid的错误保护的节能存储器组织。在这种组织中，每个存储设备作为一个独立的存储模块来服务于整个内存请求，并支持错误检测和错误恢复。它依赖于现代存储设备的高数据速率，以尽量减少增加的数据传输时间对性能的影响。RAIMD提供类似Chipkill的芯片级错误保护，但具有显著的节能效果。我们的仿真结果表明，在SPEC2017多核工作负载的DDR5-4800内存系统上，RAIMD可以平均节省26.3%的内存能量，而性能开销仅为5.3%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Computer Architecture Letters COMPUTER SCIENCE, HARDWARE & ARCHITECTURE-

CiteScore

4.60

自引率

4.30%

发文量

期刊介绍： IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.