A 2.28mW 100 MS/s 10-bit ping-pong configuration SAR-assisted pipeline ADC

Abstract

This paper presents a new successive approximation register (SAR)-assisted pipeline analog-to-digital converter (ADC). The coarse stage digital-to-analog converter (DAC) of the proposed ADC is divided into three separate capacitor arrays (a small-DAC and two big-DACs) to increase the sampling rate while simultaneously reducing the power consumption. The small-DAC performs the low-power coarse conversion, and the two big-DACs generate low-noise residue voltage in a ping-pong configuration, reducing the power consumption of the residue amplification. The big-DACs are not involved in the coarse conversion. So, any mismatch between them does not significantly degrade the overall linearity. The unit capacitors of the CDACs are determined according to a comprehensive analysis, including the overall input-referred noise, the bandwidth mismatch, and the static nonlinearity associated with the ping-pong configuration. The proposed ADC is designed and simulated in a 65 nm CMOS technology over process variations. At 1.2 V supply, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.1 dB and a spurious-free dynamic range (SFDR) of 67.3 dB for a Nyquist frequency input sampled at 100 MS/s. The total power consumption is 2.28 mW, resulting in a Walden figure of merit (FoM) of 43 fJ/conversion-step.